The core-count race in server central processing units (CPUs) has moved past 200 cores and is approaching 300. As Intel and AMD leverage chiplet designs and advanced packaging to sharply increase cores per processor, the competitive landscape is shifting against the Arm architecture camp, which once drew attention for its high-density core configurations. How quickly chips can be connected to one another, rather than raw core counts, has emerged as the variable that will determine the success of next-generation server CPUs.
The most eye-catching product is Clearwater Forest, the codename for Intel’s latest Xeon 6+ family. Intel has combined twelve 24-core dies through advanced packaging to achieve a 288-core configuration. That is double the scale of the previous-generation Xeon 6 E-core, which was a single 144-core die. Compared with AMD’s sixth-generation EPYC “Venice,” which offers up to 256 cores using high-density “Zen 6c” cores, Intel leads in maximum core count.
Intel plans to widen the gap further with Diamond Rapids, its next-generation P-core-based Xeon slated for launch in 2027. The product groups four core chiplets, each containing 16 cores, into a single “compute building block,” and combines up to four such blocks to deliver 256 P-cores. Compared with AMD’s “Zen 6,” it has more cores per chiplet and more than double the P-cores per processor.
Behind the two companies’ ability to increase core counts indefinitely is progress in packaging technology. Using silicon bridges or stacked connections, data movement between chips can be brought close to on-die levels. This largely offsets the workload-specific efficiency degradation that earlier chiplet approaches suffered. Intel began fully adopting chiplets and advanced packaging with its fourth-generation Xeon “Sapphire Rapids,” while AMD extended packaging technologies such as the Elevated Fan-Out Bridge (EFB), previously used in its GPU lineup, to CPUs with its sixth-generation EPYC “Venice.”
| Category | Intel Clearwater Forest | Intel Diamond Rapids | AMD EPYC Venice |
|---|---|---|---|
| Max cores | 288 cores (E-cores) | 256 cores (P-cores) | 256 cores (Zen 6c) |
| Die configuration | Twelve 24-core dies | Four 16-core chiplets × up to 4 blocks | 8 CCDs + 2 IODs |
| SMT support | Not disclosed | Not supported | Supported (up to 512 threads) |
| Launch timing | Shipping | Scheduled for 2027 | Shipping |
Note: Detailed SKUs and clock speeds for Intel’s Diamond Rapids have not yet been disclosed.
Intel recently unveiled the physical package of Diamond Rapids for the first time at a technology event hosted by China’s Tencent. The structure combines compute dies made on the 18A-P process with input/output (I/O) dies made on the Intel 3 process, and uses the LGA 9324 socket and the “Oak Stream” platform. It also supports 16-channel DDR5 memory, PCIe 6.0, and up to 1.28GB of shared last-level cache (LLC). However, Diamond Rapids does not support simultaneous multithreading (SMT), so its core count and thread count are the same. Intel plans to reintroduce SMT in its 2028 successor, “Coral Rapids.”
On the AMD side, verification is emerging on whether higher core counts translate into actual performance. In a benchmark comparing 256-core EPYC 9996 and 96-core high-clock EPYC 9686F processors in dual-socket configurations with SMT turned on and off, overall performance improved by about 29% and 34%, respectively, when SMT was enabled. Combined dual-socket power consumption rose by 30 to 50W, but performance-per-watt actually improved. In Liquid-DSP in particular, the 9996 and 9686F recorded performance gains of 44% and 56%, respectively.
The situation for the Arm camp has become relatively narrower. Ampere’s “AmpereOne” lineup, noted for high-performance multicore designs, tops out at 192 cores, leaving it behind the latest x86 products in core count. Arm’s AGI CPU combines two dies to offer up to 136 cores, while Nvidia’s Vera CPU packs 88 Arm-compatible custom cores onto a single die. Instead, these products pursue strategies emphasizing per-core capability, power efficiency, and bandwidth among cores, memory, and interfaces.
The impact of this competition on data center purchasing decisions will not be determined by core counts alone. Diamond Rapids is known to have a maximum thermal design power (TDP) of up to 650W, making effective performance that can offset power and cooling costs the key issue. For Intel, the burden is also significant in that the 18A-P process is its first stage for validation in the high-performance data center market. AMD is emphasizing that it manufactures its compute dies on Taiwan Semiconductor Manufacturing’s N2/N2P processes. As both companies support 16-channel memory, PCIe 6.0, and memory bandwidth of up to 1.6TB/s, future comparisons are expected to shift toward single-core performance, memory latency, and performance-per-watt.
As AI agents increase automated tasks, the role of server CPUs is growing again. This is because tasks that are difficult to delegate to GPUs, such as tool calling, data retrieval, and task scheduling, are increasing. Intel positions Diamond Rapids as a CPU for “agentic AI” infrastructure and emphasizes support for AMX and AVX 10.2 instructions. The company said it has demonstrated roughly 1.3 to 3.4 times the performance of existing AVX-512 in small language model inference. Tencent is already converting some of its cloud infrastructure from Xeon 6 to Xeon 6+ based on Clearwater Forest, and said it can run more than 350 sandboxes simultaneously on the platform and generate more than 100,000 within minutes.